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19:4219:42, 19 May 2024 diff hist −2‎ Athlon ‎No edit summary Tag: Visual edit
18:4918:49, 19 May 2024 diff hist +3‎ Slot A ‎ The DEC ALPHA EV6 is in fact a DDR CPU bus. However, it uses 50 - 66Mhz base clockrate, and is capable of 100-133MT/s. https://www.anandtech.com/show/741/3 current Tag: Visual edit
18:4318:43, 19 May 2024 diff hist +31‎ Pentium Dual-Core ‎ Article described pentium dual core as using SDRAM (PC100-133), corrected to Double-datarate SDRAM and linked to correct article. current Tag: Visual edit
18:4018:40, 19 May 2024 diff hist +18‎ Pentium ‎ →‎Pentium M: CPU architecture FSB speed is listed with "MT/s" transfer speed units, the bus is in-fact a hot rodded P6 chip GPTL and it its clock rate is 400-533Mhz, this is can be expressed as 400MT/s as well, but this causes confusion with P4 and Mobile P4 and later CPUs like Core Solo / Duo and Core 2 Solo / Duo which use DDR FSB technology. This is significant because the P6 chip at the time didn't like non-parity clock rates with memory controllers Tag: Visual edit
18:3418:34, 19 May 2024 diff hist −36‎ Athlon ‎No edit summary Tag: Visual edit
18:3418:34, 19 May 2024 diff hist +11‎ Athlon ‎ →‎Athlon XP (2001–2003) Tag: Visual edit
18:1918:19, 19 May 2024 diff hist −30‎ Athlon ‎ →‎Athlon Classic (1999): FSB falsely described as "double-pumped". No, DEC ALPHA EV6 bus is from the mid-1990s and incapable of bit-doubling per clock cycle data transfer modes. STOP VANDALIZING ARTICLES REPLACING "Mhz" wiith "MT/s" ASSUMING SYSTEMS THAT DO NOT HAVE THIS TECHNOLOGY NEED THIS RECENT UNIT OF MEASUREMENT AND ASSUMING THAT FSB HAS ALWAYS MEANT DIRECT ACCESS TO MEMORY CONTROLLER WHICH ISN'T INTEGRATED IN OLDER ARCHITECTURES Tag: Visual edit
18:1618:16, 19 May 2024 diff hist +34‎ Athlon ‎ XP CPU FSB erroniously described as 266-400MT/s. The Athlon uses DEC ALPHA EV6 CPU bus which is incapable of DDR data transfer. The FSB connects the CPU to the Northbridge, which then has a separate memory controller that talks to the memory chips with DDR transfers. The FSB is not DDR at any point, and the reason why these systems didn't benefit from dual-channel or DDR memory speeds significantly was because of this bottleneck. Only incresing FSB true clockrate increased performance Tag: Visual edit

19 May 2024